The 69th Annual IEEE International Electron Device Meeting is ready to start out on 9 December, and the convention teaser reveals that researchers have been extending the roadmap for numerous applied sciences, notably these used to make CPUs and GPUs.
Because chip corporations can’t carry on rising transistor density by cutting down chip options in two dimenstions, they’ve moved into the third dimension by stacking chips on high of one another. Now they’re working to construct transistors on high of one another inside these chips. Next, it seems probably, they’ll squeeze nonetheless extra into the third dimension by designing 3D circuits with 2D semiconductors, similar to molybdenum disulfide. All of those applied sciences will probably serve machine studying, an software with an ever-growing urge for food for processing energy. But different analysis to be offered at IEDM reveals that 3D silicon and 2D semiconductors aren’t the one issues that may preserve neural networks buzzing.
3D Chip Stacking
Increasing the variety of transistors you’ll be able to squeeze right into a given space by stacking up chips (referred to as chiplets on this case) is each the current and way forward for silicon. Generally, producers are striving to extend the density of the vertical connections between chips. But there are problems.
One is a change to the location of a subset of chip interconnects. Beginning as quickly as late 2024 chipmakers will begin constructing energy supply interconnects beneath the silicon, leaving knowledge interconnects above. This scheme, referred to as bottom energy supply, has all kinds of penalties that chip corporations are figuring out. It seems to be like Intel might be speaking about bottom energy’s penalties for 3D gadgets [see below for more on those]. And imec will study the results for a design philosophy for 3D chips referred to as system know-how cooptimization (STCO). (That’s the concept future processors might be damaged up into their primary capabilities, every operate might be by itself chiplet, these chiplets will every be made with the right know-how for the job, and then the chiplets might be reassembled right into a single system utilizing 3D stacking and different superior packaging tech.) Meanwhile, TSMC will handle a long-standing fear in 3D chip stacking—tips on how to get warmth out of the mixed chip.
[See the May 2022 issue of IEEE Spectrum for more on 3D chip stacking technologies, and the September 2021 issue for background on backside power.]
Complementary FETs and 3D Circuits
TSMC is detailing a complementary FET (CFET) that stacks an nFET on high of a pFET.
TSMC
With main producers of superior chips transferring to some type of nanosheet (or gate-all-around) transistor, analysis has intensified on the gadget that can observe—the monolithic complementary subject impact transistor, or CFET. This gadget, as Intel engineers defined within the December 2022 concern of IEEE Spectrum, builds the 2 flavors of transistor wanted for CMOS logic—NMOS and PMOS—on high of one another in a single, built-in course of.
At IEDM, TSMC will exhibit its efforts towards CFETs. They declare enhancements in yield, which is the fraction of working gadgets on a 300-mm silicon wafer, and in cutting down the mixed gadget to extra sensible sizes than beforehand demonstrated.
Meanwhile, Intel researchers will element an inverter circuit constructed from a single CFET. Such circuits may doubtlessly be half the dimensions of their peculiar CMOS cousins. Intel will even clarify a brand new scheme to provide CFETs which have completely different numbers of nanosheets of their NMOS and PMOS parts.
2D Transistors
Metal contacts mould across the fringe of a 2D semiconuctor (MoS2) to create a lower-resistance connection.
TSMC
Scaling down nanosheet transistors (and CFETs, too) will imply ever-thinner ribbons of silicon on the coronary heart of transistors. Eventually, there gained’t be sufficient atoms of silicon to do the job. So researchers are turning to supplies which can be semiconductors even in a layer that’s only one atom thick.
Three issues have dogged the concept 2D semiconductors may take over from silicon. One is that it’s been very tough to provide (or switch) a defect-free layer of 2D semiconductor. The second is that the resistance between the transistor contacts and the 2D semiconductor has been means too excessive. And lastly, for CMOS you want a semiconductor that may conduct each holes and electrons equally effectively, however no single 2D semiconductor appears to be good for each. Research to be offered at IEDM addresses all three in a single type or one other.
TSMC will current analysis into stacking one ribbon of 2D semiconductor atop one other to create the equal of a 2D-enabled nanosheet transistor. The efficiency of the gadget is unprecedented in 2D analysis, the researchers say, and one key to the outcome was a brand new, wrap-around form for the contacts, which lowered resistance.
TSMC and its collaborators will even current analysis that manages to provide 2D CMOS. It’s executed by rising molybdenum disulfide and tungsten diselenide on separate wafers and then transferring chip-size cutouts of every semiconductor to type the 2 forms of transistors.
Memory Solutions for Machine Learning
Researchers in China constructed a machine studying chip that integrates layers of carbon nanotube transistors, silicon, and reminiscence (RRAM).
Tsinghua University/Peking University
Among the most important points in machine studying is the motion of information. The key knowledge concerned are the so-called weights and activations that outline the energy of the connections between synthetic neurons in a single layer and the data that these neurons will cross to the following layer. Top GPUs and different AI accelerators prioritize this downside by retaining knowledge as shut as they will to the processing parts. Researchers have been engaged on a number of methods to do that, similar to transferring a few of the computing into the reminiscence itself and stacking reminiscence parts on high of computing logic.
Two cutting-edge examples caught my eye from the IEDM agenda. The first is using analog AI for transformer-based language fashions (ChatGPT and the like). In that scheme, the weights are encoded as conductance values in a resistive reminiscence component (RRAM). The RRAM is an integral a part of an analog circuit that performs the important thing machine studying calculation, multiply and accumulate. That computation is finished in analog as a easy summation of currents, doubtlessly saving large quantities of energy.
IBM’s Geoff Burr defined analog AI in depth within the December 2021 concern of IEEE Spectrum. At IEDM, he’ll be delivering a design for tactics analog AI can deal with transformer fashions.
Another attention-grabbing AI scheme developing at IEDM originates with researchers at Tsinghua University and Peking University. It’s primarily based on a three-layer system that features a silicon CMOS logic layer, a carbon nanotube transistor and RRAM layer, and one other layer of RRAM made out of a special materials. This mixture, they are saying, solves a knowledge switch bottleneck in lots of schemes that search to decrease the ability and latency of AI by constructing computing in reminiscence. In exams it carried out a normal picture recognition job with the same accuracy to a GPU however nearly 50 instances sooner and with about 1/fortieth the vitality.
What’s significantly uncommon is the 3D stacking of carbon nanotube transistors with RRAM. It’s a know-how the U.S. Defense Advanced Research Projects Agency spent tens of millions of {dollars} growing right into a industrial course of at SkyWater Technology Foundry. Max Shulaker and his colleagues defined the plan for the tech within the July 2016 concern of IEEE Spectrum. His staff constructed the primary 16-bit programmable nanotube processor with the know-how in 2019.
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