In context: Nvidia CEO Jensen Huang has persistently proclaimed the demise of Moore’s Law in current years. Although his counterparts at AMD and Intel maintain differing opinions, a current presentation from Google seems to align with Huang’s perspective. This alignment may additionally assist elucidate TSMC’s tendencies over the previous a number of years.
The tech business incessantly discusses how a lot time, if any, Moore’s Law has left. Google’s head of IC packaging, Milind Shah, lately supported a previous assertion that the development, which has served as a vital guidepost for the tech business, led to 2014.
In 1965, the late Intel co-founder Gordon Moore theorized that the variety of transistors per sq. inch on a circuit board would double about each two years. The concept, named after him, has principally held quick within the almost six a long time since however has lately confronted turbulence.
In 2014, MonolithIC CEO Zvi Or-Bach famous that the price of 100-million-gate transistors, which had beforehand been steadily falling, hit all-time low on the then-recent 28nm node. Semiconductor Digest experiences that Shah, talking on the 2023 IEDM convention, supported Or-Bach’s declare with a chart exhibiting that 100M gate costs have remained flat ever since, indicating that transistors have not gotten any cheaper within the final decade.
Although chipmakers proceed to shrink semiconductors and pack extra of them onto more and more highly effective chips, costs and energy consumption have elevated. Nvidia CEO Jensen Huang has tried to clarify this development by proclaiming the demise of Moore’s Law a number of instances since 2017, stating that extra highly effective {hardware} will inevitably price extra and require extra vitality.
Some have lately accused the Nvidia CEO of constructing excuses for the rising costs of Nvidia graphics playing cards. (*10*), the heads of AMD and Intel admit that Moore’s Law has at the least slowed down however declare that they’ll nonetheless obtain significant efficiency and effectivity beneficial properties from progressive strategies like 3D packaging.
However, the evaluation from Or-Bach and later Shah may align with TSMC’s wafer worth hikes, which sharply accelerated after 28nm in 2014. According to DigiTimes, the Taiwanese large’s cost-per-wafer doubled over the following two years with the introduction of 10nm in 2016. The outlet estimated that the newest 3nm wafers may price $20,000.
As TSMC and its rivals intention towards 2nm and 1nm within the coming years, additional evaluation signifies that many of the semiconductor business’s current development comes from rising wafer costs. Despite wafer gross sales falling within the final couple of years, the common worth of TSMC’s wafers stored growing.